Semiconductor manufacturers currently employ two primary technologies for central processing unit (CPU) packages. The first is referred to as pin grid array (PGA) sockets and the second is commonly referred to as land grid array (LGA) sockets.
Pin Grid Array sockets use high strength pin grid arrays attached the bottom of the package which are then engaged into a pin grid array socket. The pins are loaded laterally within the socket which adds height, cost and complexity to the socket. The pins also add cost to the package. PGA packages typically have a greater assembly and material cost due to the pins. In addition, there are limitations on the pin pitch and number of pins that can realistically be manufactured.
LGA packages may be less costly since there may be no holes, rather, pins on the LGA touch contact points on the underside of the CPU and are retained in the socket by either an integral loading scheme such as the direct socket loading (DSL) for socket T or an independent loading mechanism (ILM) with a back plate as adopted for socket B. Socket T and Socket B refer to two types of currently used socket variations. LGA use lands on the bottom of the package but the contacts need a relatively high normal force throughout the life of the socket to maintain electrical continuity. The high normal force usually requires a relatively expensive loading solution for each socket and historically a load spreader or integrated heat spreader has been used to distribute the enabling load across the array of the contacts. The load/heat spreaders add cost to the package and the socket loading mechanisms add cost the socket/platform.
Thus, semiconductor manufacturers are constantly striving to find affordable new ways to secure a CPU reliably in a confined area.